IIT Delhi demonstrates a university-built programmable micro-GPU on FPGA as AI demand lifts phone prices

The news

New Delhi, September 25. Researchers in the Department of Electrical Engineering at IIT Delhi claim to have developed a programmable micro-graphics processing unit (GPU) designed in India, which they say could eventually enable locally designed graphics hardware for low-cost embedded devices, The Indian Express reports. A GPU is a processor built to do many simple calculations at the same time, which suits drawing images and, in larger forms, training AI models. All GPUs are currently imported. “To the best of our knowledge, this is the first working, demonstrable indigenously designed micro-GPU from a university in India,” one of the researchers said. The chip is meant for graphics and display, not high-end AI computing. Suggested uses include industrial control displays, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats and educational e-book readers. The system currently runs on a Spartan-7 Field Programmable Gate Array (FPGA), a chip whose internal circuits can be rewired by software after manufacture, rather than as a standalone silicon chip. The hardware was described in RTL, the code specifying how data moves between registers. The design could also be converted into an Application-Specific Integrated Circuit (ASIC), meaning the processor would be manufactured as a dedicated silicon chip; the work is still at the FPGA stage. M Tech students Nammi Akash and M Ravi Teja led the project under Professors Jayadeva and Kaushik Saha. The team is now exploring an 8-16-core vector-style graphics processor, an optimised compiler and graphics software toolchain, and a proof of concept on a 65-nanometre ASIC process. The same day, The Hindu reported from New Delhi on the consumer end of the chip market, taking forward this magazine’s September 23 card on the memory-chip “supercycle”. Because AI companies and data centres are buying memory chips, phone makers — the paper obtained notices from Vivo, Samsung, Realme, Oppo, Nothing, Poco and Xiaomi through the All India Mobile Retailers Association (AIMRA) — have sent retailers progressively larger price-hike notices since February. The latest tranche ranges from ₹1,000 to ₹5,000, and some budget handsets have more than doubled in price. AIMRA’s founder chairman Kailash Lakhyani said companies expect the situation to last till 2028 or even 2030. Counterpoint Research said on Thursday that global sub-$200 smartphone shipments are forecast to fall about 40% between 2025 and 2030. The syllabus link is GS3 on indigenisation of technology and developing new technology.

Static syllabus linkage

1. A GPU wins by doing many simple things at once, a CPU by doing complex things in sequence. A central processing unit (CPU) has a few powerful cores optimised to run varied instructions quickly one after another, which suits operating systems and general software. A graphics processing unit (GPU) has many simpler cores that apply the same operation to large amounts of data in parallel, originally to calculate the colour of millions of pixels. The same parallelism suits the matrix multiplications at the heart of machine learning, which is why large GPUs became the engine of the AI boom. A micro-GPU of the IIT Delhi kind targets small displays and embedded devices, where low power and cost matter more than raw speed.
2. An FPGA proves a design; an ASIC turns it into a product. A Field Programmable Gate Array is a chip containing blocks of logic whose connections can be configured after manufacture, so the same FPGA can host many designs. An Application-Specific Integrated Circuit is fabricated for one design, which makes it faster, smaller and cheaper per unit but requires heavy one-time costs for masks and fabrication. Designers therefore describe hardware in a hardware description language at the register-transfer level (RTL), test it on an FPGA, and move to an ASIC only when volumes justify it. The process node, such as 65 nanometres, refers to the generation of manufacturing technology; older nodes are cheaper and adequate for many embedded chips.
3. The India Semiconductor Mission funds fabs, packaging and design. The Union Cabinet approved the Semicon India Programme in December 2021 with an outlay of ₹76,000 crore, and the India Semiconductor Mission under the Ministry of Electronics and Information Technology implements it. It supports semiconductor fabs, display fabs, compound semiconductors and assembly, testing, marking and packaging (ATMP/OSAT) units, and runs a Design Linked Incentive (DLI) scheme that offers financial support and access to design infrastructure to domestic start-ups and firms designing chips and IP cores. The Chips to Startup programme funds chip-design training and projects in academic institutions. Indigenous processors such as SHAKTI, developed at IIT Madras, and VEGA, developed by C-DAC, are built on the open RISC-V instruction set, which requires no licence fee.
4. Memory chips are the commodity layer of the AI boom. Dynamic Random-Access Memory (DRAM) is the working memory of phones and computers; it is volatile, losing data when power is off, unlike NAND flash storage. High Bandwidth Memory (HBM) stacks several DRAM dies vertically and places them next to an AI processor, giving the enormous data throughput that AI training needs. The market is dominated by a small number of manufacturers, notably Samsung, SK Hynix and Micron, so when they divert capacity to high-margin HBM for data centres, supply of ordinary DRAM for phones tightens. The IndiaAI Mission, approved in 2024, subsidises access to GPU compute for Indian researchers and start-ups, but those GPUs and their memory are imported.

Why UPSC loves this

1. The GS3 syllabus asks about indigenisation of technology. UPSC has asked why India lags in semiconductor manufacturing and what the India Semiconductor Mission seeks to achieve. A university GPU demonstration is a concrete example of the design layer, where India has talent but little intellectual property of its own. Answers that separate design, fabrication and packaging score better than generic answers about “chips”.
2. Prelims tests the vocabulary of computing hardware. Questions on terms such as RISC-V, quantum computing and AI chips have appeared, and the difference between FPGA and ASIC, or CPU and GPU, is a natural next step. The memory-chip story adds DRAM and HBM, which appear repeatedly in current affairs on the AI supply chain.
3. Global supply chains affecting household prices fit GS3 economy questions. The phone price story shows how a demand shock in one sector, AI data centres, reaches Indian consumers through a concentrated supply chain. This is useful for questions on inflation drivers, the digital divide and the resilience of electronics manufacturing under the Production Linked Incentive scheme.

Analysis

1. The achievement is design capability, not a product, and that is the right place to start. A micro-GPU on a Spartan-7 FPGA will not compete with commercial graphics chips, and the researchers do not claim it will. Its value is that an Indian team now owns a programmable graphics architecture, its RTL and, if they build it, its compiler. Intellectual property of this kind is what India lacks most: the country has many chip designers working for foreign companies, but few Indian-owned designs. The honest limit is that a GPU without a software ecosystem is hard to use, which is why the planned compiler and toolchain matter as much as the silicon.
2. Targeting e-rickshaws and fishing boats is a smart market choice. The team is aiming at low-cost embedded displays, a segment that global chip firms serve with cheap imported parts but do not design for. Indian products such as e-rickshaw dashboards, small-boat navigation terminals and school e-readers need modest graphics at very low cost and long product life. A domestic design that can be tailored for these uses, and supported locally, has a real niche. The risk is scale: these markets are price-sensitive, and an ASIC only becomes cheaper than an off-the-shelf part at large volumes, which a university project cannot guarantee without industry partners.
3. The phone price shock shows the cost of being a price-taker in chips. India assembles most of the phones it sells but designs and fabricates almost none of the memory inside them. When memory makers shift capacity to HBM for AI data centres, Indian buyers pay ₹1,000 to ₹5,000 more per handset, and some budget models have more than doubled. The Hindu’s report that 20% of customers are settling for less powerful or second-hand phones is a digital-divide story, because the budget phone is the main internet device for poorer households. No university GPU fixes this in the near term, but it illustrates why policy is moving from assembly subsidies to design and fabrication.
4. Price data from retailers should be read with care. The figures come from an association of retailers, and Mr. Lakhyani also said some retailers are earning higher margins, from 3.85% to over 14% on some Samsung models, on stock bought at older prices. Retailers have an interest in highlighting falling sales, and the claim that only one or two of the 10 or 15 daily visitors buy a phone is a single south Delhi shop’s experience. The forecast of a fall of about 40% in global sub-$200 shipments comes from Counterpoint, not from Indian data. The trend is real, but its size for India is not yet measured, and the “rumour” of a GST cut on phones mentioned in the report should not be treated as policy.
5. University chip projects need a path to fabrication, not just grants. The team’s next step, a 65-nanometre ASIC proof of concept, requires access to a fabrication facility and costly mask sets. India’s design-linked incentives and academic chip-design programmes are meant to provide exactly this, but projects often stall between a successful FPGA demonstration and first silicon. Pooled multi-project wafer runs, in which many designs share one fabrication run, lower the cost for academic groups. If the new Indian fabs under construction offer such shared runs at older nodes, university designs like this one could reach silicon in months rather than years.

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